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NB100LVEP222 2.5 V/3.3 V 1:15 Differential ECL/PECL /1//2 Clock Driver
The NB100LVEP222 is a low skew 1:15 differential /1//2 ECL fanout buffer designed with clock distribution in mind. The LVECL/LVPECL input signal pairs can be used in a differential configuration or single-ended (with VBB output reference bypassed and connected to the unused input of a pair). Either of two fully differential clock inputs may be selected. Each of the four output banks of 2, 3, 4, and 6 differential pairs may be independently configured to fanout 1X or 1/2X of the input frequency. When the output banks are configured with the B1 mode, data can also be distributed. The LVEP222 specifically guarantees low output to output skew. Optimal design, layout, and processing minimize skew within a device and from lot to lot. This device is an improved version of the MC100LVE222 with higher speed capability and reduced skew. The fsel pins and CLK_Sel pin are asynchronous control inputs. Any changes may cause indeterminate output states requiring an MR pulse to resynchronize any 1/2X outputs (See Figure 3). Unused output pairs should be left unterminated (open) to reduce power and switching noise. The NB100LVEP222, as with most ECL devices, can be operated from a positive VCC/VCC0 supply in LVPECL mode. This allows the LVEP222 to be used for high performance clock distribution in +2.5/3.3 V systems. In a PECL environment series or Thevenin line, terminations are typically used as they require no additional power supplies. For more information on using PECL, designers should refer to Application Note AN1406/D. For a SPICE model, refer to Application Note AN1560/D. The VBB pin, an internally generated voltage supply, is available to this device only. For single-ended LVPECL input conditions, the unused differential input is connected to VBB as a switching reference voltage. VBB may also rebias AC coupled inputs. When used, decouple VBB and VCC/VCC0 via a 0.01 mF capacitor and limit current sourcing or sinking to 0.5 mA. When not used, VBB should be left open. Single-ended CLK input operation is limited to a VCC/VCC0 3.0 V in LVPECL mode, or VEE v -3.0 V in NECL mode.
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MARKING DIAGRAM*
52-LEAD LQFP THERMALLY ENHANCED CASE 848H FA SUFFIX A WL YY WW G
NB100 LVEP222 AWLYYWWG
52 1
= Assembly Location = Wafer Lot = Year = Work Week = Pb-Free Package
*For additional information, see Application Note AND8002/D
ORDERING INFORMATION
Device NB100LVEP222FA Package LQFP-52 Shipping 160 Units/Tray
NB100LVEP222FAR2 LQFP-52 1500/Tape & Reel NB100LVEP222FAG LQFP-52 (Pb-Free) 160 Units/Tray
* * * * *
20 ps Output-to-Output Skew 85 ps Part-to-Part Skew Selectable 1x or 1/2x Frequency Outputs LVPECL Mode Operating Range: VCC/VCC0 = 2.375 V to 3.8 V with VEE = 0 V NECL Mode Operating Range: VCC/VCC0 = 0 V with VEE = -2.375 V to -3.8 V Internal Input Pulldown Resistors
NB100LVEP222FARG LQFP-52 1500/Tape & Reel (Pb-Free) For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specification Brochure, BRD8011/D.
* * Performance Upgrade to ON Semiconductor's MC100LVE222 * VBB Output * Pb-Free Packages are Available*
*For additional information on our Pb-Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D.
(c) Semiconductor Components Industries, LLC, 2005
1
October, 2005- Rev. 9
Publication Order Number: NB100LVEP222/D
NB100LVEP222
VCC0 VCC0 VCC0 27 26 25 24 23 22 21
Qc0
Qc0
Qc1
Qc1
Qc2
Qc2
Qc3
Qc3
NC 29
VCC0 Qb2 Qb2 Qb1 Qb1 Qb0 Qb0 VCC0 Qa1 Qa1 Qa0 Qa0 VCC0
39 40 41 42 43 44 45 46 47 48 49 50 51 52 1
38
37
36
35
34
33
32
31
30
NC 28
Qd0 Qd0 Qd1 Qd1 Qd2 Qd2 Qd3 Qd3 Qd4 Qd4 Qd5 Qd5 VCC0
NB100LVEP222
20 19 18 17 16 15 14
2
3
4
5
6
7
8
9
10
11
12
13
CLK0
CLK0
MR
CLK1
CLK1
fseld L
VBB
CLK_Sel
fsela
fselb
All VCC, VCC0, and VEE pins must be externally connected to appropriate Power Supply to guarantee proper operation.VCC pin internally connected to VCC0 pins. The thermally conductive exposed pad on package bottom (see package case drawing) must be attached to a heat-sinking conduit. This exposed pad is electrically connected to VEE internally.
Figure 1. 52-Lead LQFP Pinout (Top View) PIN DESCRIPTION
PIN CLK0*, CLK0** CLK1*, CLK1** CLK_Sel* MR* Qa0:1, Qa0:1 Qb0:2, Qb0:2 Qc0:3, Qc0:3 Qd0:5, Qd0:5 fseln* VBB VCC, VCC0 VEE*** NC FUNCTION ECL Differential Input Clock ECL Differential Input Clock ECL Clock Select ECL Master Reset ECL Differential Outputs ECL Differential Outputs ECL Differential Outputs ECL Differential Outputs ECL 1 or 2 Select Reference Voltage Output Positive Supply, VCC = VCC0 Negative Supply No Connect Input MR CLK_Sel fseln
FUNCTION TABLE
Function H Reset CLK1 /2
fselc
VCC
Active CLK0 /1
* Pins will default LOW when left open. ** Pins will default HIGH when left open. *** The thermally conductive exposed pad on the bottom of the package is electrically connected to VEE internally.
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VEE
NB100LVEP222
MR CLK0 CLK0 /1 CLK1 CLK1 /2 2 Qa0:1 Qa0:1
CLK_SEL
VBB fsela 3 Qb0:2 Qb0:2 fselb 4 VCC/VCC0 VEE Qc0:3 Qc0:3 fselc 6 Qd0:5 Qd0:5 fseld
Figure 2. Logic Diagram
CLK
MR
Q (B2)
Q (B1)
Figure 3. Master Reset (MR) Timing Diagram
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NB100LVEP222
ATTRIBUTES
Characteristics Internal Input Pulldown Resistor Internal Input Pullup Resistor ESD Protection Human Body Model Machine Model Charged Device Model Value 75 kW 37.5 kW > 2 kV > 200 V > 2 kV Level 3 Oxygen Index: 28 to 34 UL 94 V-0 @ 0.125 821 Devices
Moisture Sensitivity (Note 1) Flammability Rating Transistor Count Meets or Exceeds JEDEC Spec EIA/JESD78 IC Latchup Test 1. For additional information, refer to Application Note AND8003/D.
MAXIMUM RATINGS (Note 2)
Symbol VCC/VCC0 VEE VI Iout IBB TA Tstg qJA qJC Tsol Parameter PECL Mode Power Supply NECL Mode Power Supply PECL Mode Input Voltage NECL Mode Input Voltage Output Current VBB Sink/Source Operating Temperature Range Storage Temperature Range Thermal Resistance (Junction-to-Ambient) (See Application Information) Thermal Resistance (Junction-to-Case) (See Application Information) Wave Solder 0 LFPM 500 LFPM 0 LFPM 500 LFPM < 2 to 3 sec @ 248C 52 LQFP 52 LQFP 52 LQFP 52 LQFP Condition 1 VEE = 0 V VCC/VCC0 = 0 V VEE = 0 V VCC/VCC0 = 0 V Continuous Surge VI VCC/VCC0 VI VEE Condition 2 Rating 6 -6 6 to 0 -6 to 0 50 100 0.5 -40 to +85 -65 to +150 35.6 30 3.2 6.4 265 Units V V V V mA mA mA C C C/W C/W C/W C/W C
2. Maximum Ratings are those values beyond which device damage may occur.
LVPECL DC CHARACTERISTICS VCC = VCC0 = 2.5 V; VEE = 0 V (Note 3)
-40C Symbol IEE VOH VOL VIH VIL VIHCMR Characteristic Power Supply Current Output HIGH Voltage (Note 4) Output LOW Voltage (Note 4) Input HIGH Voltage (Single-Ended) (Note 5) Input LOW Voltage (Single-Ended) (Note 5) Input HIGH Voltage Common Mode Range (Differential Configuration) (Note 6) (Figure 5) Input HIGH Current Input LOW Current CLK CLK 0.5 -150 Min 100 1355 555 1335 555 1.2 Typ 125 1480 680 Max 150 1605 900 1620 900 2.5 Min 104 1355 555 1335 555 1.2 25C Typ 130 1480 680 Max 156 1605 900 1620 900 2.5 Min 112 1355 555 1275 555 1.2 85C Typ 140 1480 680 Max 168 1605 900 1620 900 2.5 Unit mA mV mV mV mV V
IIH IIL NOTE: 3. 4. 5. 6.
150 0.5 -150
150 0.5 -150
150
mA mA
100LVEP circuits are designed to meet the DC specifications shown in the above table, after thermal equilibrium has been established. The circuit is in a test socket or mounted on a printed circuit board and transverse air flow greater than 500 lfpm is maintained. Input and output parameters vary 1:1 with VCC/VCC0. VEE can vary + 0.125 V to -1.3 V. All loading with 50 W to VCC/VCC0 - 2.0 V. Do not use VBB Pin #10 at VCC/VCC0 < 3.0 V (see AND8066). VIHCMR min varies 1:1 with VEE, VIHCMR max varies 1:1 with VCC/VCC0. The VIHCMR range is referenced to the most positive side of the differential input signal.
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NB100LVEP222
LVPECL DC CHARACTERISTICS VCC = VCC0 = 3.3 V; VEE = 0.0 V (Note 7)
-40C Symbol IEE VOH VOL VIH VIL VBB VIHCMR Characteristic Power Supply Current Output HIGH Voltage (Note 8) Output LOW Voltage (Note 8) Input HIGH Voltage (Single-Ended) Input LOW Voltage (Single-Ended) Output Reference Voltage (Note 9) Input HIGH Voltage Common Mode Range (Differential Configuration) (Note 10) (Figure 5) Input HIGH Current Input LOW Current CLK CLK 0.5 -150 Min 100 2155 1355 2135 1355 1775 1.2 1875 Typ 125 2280 1480 Max 150 2405 1700 2420 1700 1975 3.3 Min 104 2155 1355 2135 1355 1775 1.2 1875 25C Typ 130 2280 1480 Max 156 2405 1700 2420 1700 1975 3.3 Min 112 2155 1355 2135 1355 1775 1.2 1875 85C Typ 140 2280 1480 Max 168 2405 1700 2420 1700 1975 3.3 Unit mA mV mV mV mV mV V
IIH IIL NOTE:
150 0.5 -150
150 0.5 -150
150
mA mA
100LVEP circuits are designed to meet the DC specifications shown in the above table, after thermal equilibrium has been established. The circuit is in a test socket or mounted on a printed circuit board and transverse air flow greater than 500 lfpm is maintained. 7. Input and output parameters vary 1:1 with VCC/VCC0. VEE can vary + 0.925 V to -0.5 V. 8. All loading with 50 W to VCC/VCC0-2.0 V. 9. Single ended input operation is limited VCC/VCC0 3.0 V in LVPECL mode. 10. VIHCMR min varies 1:1 with VEE, VIHCMR max varies 1:1 with VCC/VCC0. The VIHCMR range is referenced to the most positive side of the differential input signal.
LVNECL DC CHARACTERISTICS VCC = VCC0 = 0.0 V; VEE = -3.8 V to -2.375 V (Note 11)
-40C Symbol IEE VOH VOL VIH VIL VBB VIHCMR Characteristic Power Supply Current Output HIGH Voltage (Note 12) Output LOW Voltage (Note 12) Input HIGH Voltage (Single Ended) Input LOW Voltage (Single Ended) Output Reference Voltage (Note 13) Input HIGH Voltage Common Mode Range (Differential Configuration) (Note 14) (Figure 5) Input HIGH Current Input LOW Current CLK CLK 0.5 -150 Min 100 -1145 -1945 -1165 -1945 -1525 -1425 Typ 125 -1020 -1820 Max 150 -895 -1600 -880 -1600 -1325 0.0 Min 104 -1145 -1945 -1165 -1945 -1525 -1425 25C Typ 130 -1020 -1820 Max 156 -895 -1600 -880 -1600 -1325 0.0 Min 112 -1145 -1945 -1165 -1945 -1525 -1425 85C Typ 140 -1020 -1820 Max 168 -895 -1600 -880 -1600 -1325 0.0 Unit mA mV mV mV mV mV V
VEE + 1.2
VEE + 1.2
VEE + 1.2
IIH IIL NOTE:
150 0.5 -150
150 0.5 -150
150
mA mA
100LVEP circuits are designed to meet the DC specifications shown in the above table, after thermal equilibrium has been established. The circuit is in a test socket or mounted on a printed circuit board and transverse air flow greater than 500 lfpm is maintained. 11. Input and output parameters vary 1:1 with VCC/VCC0. 12. All loading with 50 W to VCC/VCC0 - 2.0 V. 13. Single ended input operation is limited VEE -3.0 V in NECL mode. 14. VIHCMR min varies 1:1 with VEE, VIHCMR max varies 1:1 with VCC/VCC0. The VIHCMR range is referenced to the most positive side of the differential input signal.
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NB100LVEP222
AC CHARACTERISTICS VCC = VCC0 = 2.375 to 3.8 V; VEE = 0.0 V or VCC = VCC0 = 0.0 V; VEE = -2.375 to -3.8 V (Note 15)
-40C Symbol VOpp Characteristic Differential Output Voltage (Figure 4) fout = 50 MHz fout = 0.8 GHz fout = 1.0 GHz Min 500 550 500 650 700 Typ 600 650 650 800 900 10 10 20 10 10 20 15 15 20 15 15 20 85 1 150 49.5 100 800 50 200 900 1200 40 40 60 40 40 60 70 70 70 70 70 70 300 5 1200 50.5 300 150 49.5 100 Max Min 500 525 425 700 700 25C Typ 600 650 650 875 900 10 10 20 10 10 20 10 10 20 10 10 20 85 1 800 50 200 1000 1200 40 40 60 40 40 60 40 40 50 40 40 50 300 4 1200 50.5 300 150 49.5 150 Max Min 500 500 400 850 700 85C Typ 600 650 600 ps 975 900 10 10 20 10 10 20 15 10 15 15 15 15 85 1 800 50 250 1150 1200 ps - Qa[0:1] - Qb[0:2] - Qc[0:3] - Qd[0:5] 40 40 60 40 40 60 ps - Qa[0:1] - Qb[0:2] - Qc[0:3] - Qd[0:5] 70 40 70 70 70 70 300 5 1200 50.5 350 ps ps mV % ps Max Unit mV
tPLH tPHL tskew
Propagation Delay (Differential Configuration) CLKx-QX MR-QXX Within-Device Skew (Note 16) (/1 Mode)
- QaN, QbN, QdN - All Outputs tskew Within-Device Skew (Note 16) (/2 Mode)
- QaN, QbN, QdN - All Outputs tskew tJITTER VPP DCO tr/tf Device-to-Device Skew (Differential Configuration) (Note 17) Random Clock Jitter (Figure 4) (RMS) Input Swing (Differential Configuration) (Note 18) (Figure 5) Output Duty Cycle Output Rise/Fall Time 20%-80%
15. Measured with LVPECL 750 mV source, 50% duty cycle clock source. All outputs loaded with 50 W to VCC/VCC0 - 2.0 V. 16. Skew is measured between outputs under identical transitions and operating conditions. 17. Device-to-Device skew for identical transitions at identical VCC/VCC0 levels. 18. VPP is the differential configuration input voltage swing required to maintain AC characteristics including tPD and device-to-device skew. 900 800 Q AMP (/ 2) 700 600 Q AMP (/ 1) 500 400 RMS JITTER 300 200 0.1 0.5 1.0 INPUT FREQUENCY (GHz) 1.5 10 9.0 8.0 RMS JITTER (ps) 7.0 6.0 5.0 4.0 3.0 2.0 1.0 0 2.0
Figure 4. Output Voltage (VOPP) versus Input Frequency and Random Clock Jitter (tJITTER) @ 255C
VOPP, OUTPUT VOLTAGE (mV)
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NB100LVEP222
VCC/VCC0(LVPECL) VIH(DIFF) VPP VIHCMR VIL(DIFF) VEE
Figure 5. LVPECL Differential Input Levels
Q Driver Device Q 50 W 50 W
D Receiver Device D
VTT VTT = VCC or VCC0 - 2.0 V
Figure 6. Typical Termination for Output Driver and Device Evaluation (Refer to Application Note AND8020 - Termination of ECL Logic Devices)
Resource Reference of Application Notes
AN1405 AND8002 AND8009 AND8020 AND8066 - - - - - ECL Clock Distribution Techniques Marking and Date Codes ECLinPS Plus Spice I/O Model Kit Termination of ECL Logic Devices Interfacing with ECLinPS
For an updated list of Application Notes, please see our website at http://onsemi.com.
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NB100LVEP222
APPLICATIONS INFORMATION Using the thermally enhanced package of the NB100LVEP222 The NB100LVEP222 uses a thermally enhanced 52-lead LQFP package. The package is molded so that a portion of the leadframe is exposed at the surface of the package bottom side. This exposed metal pad will provide the low thermal impedance that supports the power consumption of the NB100LVEP222 high-speed bipolar integrated circuit and will ease the power management task for the system design. In multilayer board designs, a thermal land pattern on the printed circuit board and thermal vias are recommended to maximize both the removal of heat from the package and electrical performance of the NB100LVEP222. The size of the land pattern can be larger, smaller, or even take on a different shape than the exposed pad on the package. However, the solderable area should be at least the same size and shape as the exposed pad on the package. Direct soldering of the exposed pad to the thermal land will provide an efficient thermal conduit. The thermal vias will connect the exposed pad of the package to internal copper planes of the board. The number of vias, spacing, via diameters and land pattern design depend on the application and the amount of heat to be removed from the package. Maximum thermal and electrical performance is achieved when an array of vias is incorporated in the land pattern. The recommended thermal land design for NB100LVEP222 applications on multi-layer boards comprises a 4 X 4 thermal via array using a 1.2 mm pitch as shown in Figure 7 providing an efficient heat removal path.
All Units mm
supply enough solder paste to fill those vias and not starve the solder joints. The attachment process for the exposed pad package is equivalent to standard surface mount packages. Figure 8, "Recommended solder mask openings", shows a recommended solder mask opening with respect to a 4 X 4 thermal via array. Because a large solder mask opening may result in a poor rework release, the opening should be subdivided as shown in Figure 8. For the nominal package standoff of 0.1 mm, a stencil thickness of 5 to 8 mils should be considered.
All Units mm 0.2 1.0
1.0 4.6 0.2
4.6 Thermal Via Array (4 X 4) 1.2 mm Pitch 0.3 mm Diameter Exposed Pad Land Pattern
Figure 8. Recommended Solder Mask Openings
4.6
Proper thermal management is critical for reliable system operation. This is especially true for high-fanout and high output drive capability products. For thermal system analysis and junction temperature calculation the thermal resistance parameters of the package is provided:
Table 1. Thermal Resistance *
LFPM 0 100 qJA 5C/W 35.6 32.8 30.0 qJC 5C/W 3.2 4.9 6.4
4.6 Thermal Via Array (4 X 4) 1.2 mm Pitch 0.3 mm Diameter Exposed Pad Land Pattern
500
Figure 7. Recommended Thermal Land Pattern
The via diameter should be approximately 0.3 mm with 1 oz. copper via barrel plating. Solder wicking inside the via may result in voiding during the solder process and must be avoided. If the copper plating does not plug the vias, stencil print solder paste onto the printed circuit pad. This will
* Junction to ambient and Junction to board, four-conductor layer test board (2S2P) per JESD 51-8 These recommendations are to be used as a guideline, only. It is therefore recommended that users employ sufficient thermal modeling analysis to assist in applying the general recommendations to their particular application to assure adequate thermal performance. The exposed pad of the NB100LVEP222 package is electrically shorted to the substrate of the integrated circuit and VEE. The thermal land should be electrically connected to VEE.
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NB100LVEP222
PACKAGE DIMENSIONS
LQFP 52 LEAD EXPOSED PAD PACKAGE CASE 848H-01 ISSUE A
M M/2 -Z-
52 1 4 PL
AJ AJ
40 39
0.20 (0.008) T X-Y Z
PLATING
-X- L
-Y- B AB
AA
J
L/2
13 14 26 27
B/2
D
REF M
0.08 (0.003)
Y T-U
DETAIL AJ-AJ 0.20 (0.008) E X-Y Z
A/2 A DETAIL AH -E- -T-
SEATING PLANE
NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MM. 3. DATUM PLANE E" IS LOCATED AT BOTTOM OF LEAD AND IS COINCIDENT WITH THE LEAD WHERE THE LEAD EXITS THE PLASTIC BODY AT THE BOTTOM OF THE PARTING PLANE. 4. DATUM X", Y" AND Z" TO BE DETERMINED AT DATUM PLANE DATUM E". BASE METAL 5. DIMENSIONS M AND L TO BE DETERMINED AT SEATING PLANE DATUM T". 6. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. ALLOWABLE PROTRUSION IS 0.25 (0.010) PER SIDE. DIMENSIONS A AND B DO INCLUDE MOLD MISMATCH AND ARE DETERMINED AT DATUM PLAND E". 7. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL NOT CAUSE THE LEAD WIDTH TO EXCEED THE MAXIMUM D DIMENSION BY MORE THAN 0.08 (0.003). DAMBAR CANNOT Z BE LOCATED ON THE LOWER RADIUS OR THE FOOT. MINIMUM SPACE BETWEEN PROTRUSION AND ADJACENT LEAD OR PROTRUSION 0.07 (0.003). DIM A B C D F G H J K L M N P R S V W AA AB AC AD AE MILLIMETERS MIN MAX 10.00 BSC 10.00 BSC 1.30 1.50 0.22 0.40 0.45 0.75 0.65 BSC 1.00 REF 0.09 0.20 0.05 0.20 12.00 BSC 12.00 BSC 0.20 REF 0_ 7_ 0_ --- --- 1.70 12 _ REF 12 _ REF 0.20 0.35 0.07 0.16 0.08 0.20 4.58 4.78 4.58 4.78 INCHES MIN MAX 0.394 BSC 0.394 BSC 0.051 0.059 0.009 0.016 0.018 0.030 0.026 BSC 0.039 BSC 0.004 0.008 0.002 0.008 0.472 BSC 0.472 BSC 0.008 REF 0_ 7_ 0_ --- --- 0.067 12 _ REF 12 _ REF 0.008 0.014 0.003 0.006 0.003 0.008 0.180 0.188 0.180 0.188
AG
G
48 PL
AG
0.10 (0.004) T
D
52 PL M
0.08 (0.003)
T X-Y
Z
V 0.05 (0.002)
S
AD
EXPOSED PAD 13 14 26 27
S
C
K AE
W N F H DETAIL AH
1 52 40
39
VIEW AG-AG
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CCCC EEEE CCCC EEEE
R
AC
P
0.25
GAGE PLANE
NB100LVEP222
ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. "Typical" parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
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NB100LVEP222/D

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